The present invention concerns the refresh of a charge stored in a cross-coupled, four transistor dynamic random access memory (DRAM).
DRAMs may be designed to have a greater density than static random access memories (SRAM). However, it is necessary to periodically refresh DRAMs to recharge memory cells.
In the prior art, DRAMs have typically been refreshed using external logic. This external logic generally includes an interval timer which determines when a refresh cycle is needed. During the refresh cycle the external logic generates refresh control signals. The control signals cause a row-address strobe (RAS) command to simultaneously be sent to DRAMs. Also, the control signals cause each DRAM to cycle through all their row addresses in order to refresh every cell.
Some DRAMs have been designed to use internal logic to perform a refresh in response to a signal from external circuitry. See, for example, Eaton, et al., A 100 Nanosecond 64K Dynamic RAM using Redundancy Techniques, 1981 ISSCC. These DRAMs include a refresh counter used to internally generate refresh addresses.
Other DRAMs have been designed with a "self-refresh" mode. See for example, Reese, et al., A 4K.times.8 Dynamic RAM with Self Refresh, 1981 ISSCC. When in self-refresh mode, the DRAM will refresh its memory cells without direction from an external circuit. However, while the DRAM is in the self-refresh mode, the DRAM locks out memory accesses.
One design of a DRAM has been referred to as a "quasi-static" RAM. See Chu, et al., A 5 Volt 4K.times.8 Quasi Static Ram, IEEE ISSCC, 1979, p. 156. Each of these DRAMs includes all refresh circuitry needed to refresh its memory cells; however, the DRAM will lock out external memory accesses which will interfere with a refresh operation. In this design, the DRAM memory cells are split into two arrays. These arrays are multiplexed so that while one of the arrays is being accessed, the other array is being refreshed. As long as there is roughly an equal number of accesses from both arrays, the DRAM is able to keep all its memory cells refreshed. However, if the there are a long string of address accesses from the same array, the DRAM will have to signal the external circuitry that it must perform an internal refresh. The DRAM locks out memory accesses and performs the refresh of the array of memory cells.
The above-discussed DRAMs all have certain disadvantages. Generally, the DRAMs require external circuitry to manage the refresh operation. When there is no refresh support internally on the DRAM, the external circuitry must include address counters and timers. When the external circuitry is minimized or eliminated, there are occasions when the DRAMs must lock out memory accesses in order to complete a refresh cycle.